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41714hkpc 20140327-s00001 no.a0145-1/34 semiconductor components industries, llc, 2014 april, 2014 ver. 1.70a http://onsemi.com ordering information see detailed ordering and shipping informa tion on page 34 of this data sheet. lc87f6ac8a overview the lc87f6ac8a is an 8-bit microcontro ller that, centered around a cpu running at a minimum bus cycle time of 83.3 ns, integrates on a single chip a numb er of hardware features such as 128k-byte flash rom (onboard programmable), 4096-byte ram, on-chip debugging function, a vacuum fluorescent display (vfd) automatic display controller/driver, a 16-bit timer/counter (may be divided into 8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timer/counter or 8-bit pwms), four 8-bit tim ers with a prescaler, a 16-bit ti mer with a prescaler (may be divided into 8-bit timers), a base timer used as a time-of-day clock, a high-speed clock counter, a system clock frequency divider, two synchronous sio* with automatic transfer capability, an asynchronous/synchronous sio, two channels of 12-bit pwm modules*, an 8-bit 15-channel ad converter, a small signal detector, and a 27-source 10-vector interrupt feature*. (* can be supported with the lc876a00 or lc876b00 series by selecting ?user options.?) features ? flash rom ? capable of onboard programming with a single 5v power supply ? on-chip debugging function ? block erasable in 128-byte units ? 131072 8 bits ? ram ? 4096 9 bits ? minimum bus cycle time ? 83.3s (at 12 mhz) v dd = 2.8 to 5.5[v] ? 250ns (at 4 mhz) v dd = 2.5 to 5.5[v] note: the bus cycle time refe rs to the rom read speed. ? minimum instruction cycle time (tcyc) ? 249.9ns (at 12 mhz) v dd = 2.8 to 5.5[v] ? 750ns (at 4 mhz) v dd = 2.5 to 5.5[v] ? package form ? qip100e (lead/halogen free type) orderin g numbe r : ENA0145 cmos lsi 8-bit withstand voltage microcontroller 128k-byte flash rom / 4096-byte ram / 100pin qip100e(14x20)
lc87f6ac8a no.a0145-2/34 ? ports ? normal withstand voltage i/o ports user option selection ports whose input/o utput can be specified in 1-bit units for lc876a00 series 32 (p1n, p70 to p73, p8n, p30 to p37, pan) for lc876b00 series 32 (p1n, p70 to p7 3, p8n, p32 to p35, si2pn, pan) port that can also be used for oscillation 1 (xt2) ? 12v max. withstand voltage i/o ports ports whose input/output can be specified in 4-bit units 8 (p0n) (in 1- bit units when configured for n-channel open drain output) ? normal withstand voltage input-only port (also used for oscillation) 1 (xt1) ? vacuum fluorescent display (vfd) driver ports large current outputs for digits 9 (s0/t0 to s8/t8) large current outputs for digits/segments 7 (s9/t9 to s15/t15) outputs for digits/segments 8 (s16 to s23) outputs for segments 24 (s24 to s47) multiplexed pin function i/o ports 8 (pfn) input ports 24 (pcn, pdn, pen) ? dedicated oscillator pins 2 (cf1, cf2) ? reset pin 1 ( ____ res) ? power pins 6 (v ss 1 to v ss 2, v dd 1 to v dd 4) ? dedicated vacuum fluorescent display driver power pin 1 (vp) ? vfd automatic display controller <1> programmable segment/digit output patterns waveform output can be switched between segment and digit output. (number of pins available for digit waveform output: 9 to 24) capable of driving large current vfds in parallel <2> provides 16-step dimmer function ? small signal detection (microphone signals, etc.) <1> counts pulses with amplitude s greater than a preset level <2> 2-bit counter ? timers ? timer 0: 16-bit timer/counter with two capture registers mode 0: 8-bit timer with an 8-bit programmable pres caler (with two 8-bit capture registers) 2 channels mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture regi sters) + 8-bit counter (with two 8-bit capture registers) mode 2: 16-bit timer with an 8-bit programmabl e prescaler (with two 16-bit capture registers) mode 3: 16-bit counter (with two 16-bit capture registers) ? timer 1: 16-bit timer/counter w ith pwm/toggle output capability mode 0: 8-bit timer with an 8-bit prescaler (with toggle output) + 8-bit timer/counter with an 8-bit prescaler (with toggle output) mode 1: 8-bit pwm with an 8-bit prescaler 2 channels mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle output) (toggle output also possible from the low-order 8 bits) mode 3: 16-bit timer with an 8-bit prescaler (with toggle output) (the low-order 8 bits can be used as pwm.)
lc87f6ac8a no.a0145-3/34 ? timer 4: 8-bit timer with a 6-bit prescaler ? timer 5: 8-bit timer with a 6-bit prescaler ? timer 6: 8-bit timer with a 6-bit prescaler (with toggle output) ? timer 7: 8-bit timer with a 6-bit prescaler (with toggle output) ? timer 8: 16-bit timer mode 0: 8-bit timer with an 8-bit prescaler 2 channels mode 1: 16-bit timer with an 8-bit prescaler *timer 8 is not supported by emulator. an on-chip debugger must be used to develop software for timer 8. ? base timer <1> the clock can be selected from among the subclock (3 2.768khz crystal oscillator), system clock, and timer 0 prescaler output. <2> interrupts are programmable in 5 different time schemes. ? high-speed clock counter <1> capable of counting clocks with a maximum clock rate of 20mhz (when 10mhz main clock is used) <2> real-time output ? serial interface ? sio0: 8-bit synchronous serial interface <1> lsb first/msb first is selectable. <2> built-in 8-bit baudrate generator (maximum transfer clock cycle: 4/3 tcyc) <3> automatic continuous data communication (1 to 256 bits, selectable in 1-bit units) (suspension and resumption of data transfer controllable in byte units) ? sio1: 8-bit asynch ronous/synchronous serial interface mode 0: synchronous 8-bit serial i/o (2- or 3-wire configuration, 2 to 512 tcyc transfer clock) mode 1: asynchronous serial i/o (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tcyc baudrate) mode 2: bus mode 1 (start bit, 8 data bits, 2 to 512 tcyc transfer clock) mode 3: bus mode 2 (start detect, 8 data bits, stop detect) ? sio2: 8-bit synchronous serial interface *availabl e in lc876b00 series compatible configuration <1> lsb first <2> built-in 8-bit baudrate generator (maximum transfer clock cycle: 4/3 tcyc) <3> automatic continuous data communication (1 to 32 bytes, selectable in byte units) ? adc: 8 bits 15 channels ? reference voltage can be selected from the v dd 1 or v dd 2 pin. ? pwm *available in lc876a00 series compatible configuration ? multifrequency 12-bit pwm 2 channels ? remote control receiver circuit (multip lexed with the p73/int3/t0in pin) <1> noise rejection function (noise filter tim e constant selectable from 1/32/128 tcyc) ? watchdog timer <1>external rc watchdog timer <2>interrupt and reset signals selectable
lc87f6ac8a no.a0145-4/34 ? interrupts: 27 sources, 10 vector addresses (lc876a00 compatible) 26 sources, 10 vector addresses (lc876b00 compatible) <1> provides three levels (low (l), high (h), and highest (x )) of multiplex interrupt control. any interrupt request of the level equal to or lower than th e current interrupt is not accepted. <2> when interrupt requests to two or more vector addresse s occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. for interrupts of the same level, the interrupt into the smallest vector address is given priority. * lc876a00 series comp atible configuration no. vector address level interrupt source 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2 / t0l / int4 4 0001bh h or l int3 / base timer / int5 5 00023h h or l t0h / int6 6 0002bh h or l t1l / t1h / int7 7 00033h h or l sio0 / t8l / t8h 8 0003bh h or l sio1 9 00043h h or l adc / mic / t6 / t7 / pwm4 / pwm5 10 0004bh h or l vfd / port 0 / t4 / t5 * lc876b00 series compatible configuration no. vector address level interrupt source 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2 / t0l / int4 4 0001bh h or l int3 / base timer / int5 5 00023h h or l t0h / int6 6 0002bh h or l t1l / t1h / int7 7 00033h h or l sio0 / t8l / t8h 8 0003bh h or l sio1 / sio2 9 00043h h or l adc / mic / t6 / t7 10 0004bh h or l vfd / port 0 / t4 / t5 ? priority levels x > h > l ? when interrupts of the same level occur at the same time, the interrupt with the smallest vector address is given priority. ? subroutine stack levels: up to 2048 levels (the stack is allocated in ram.) ? high-speed multiplication division instructions ? 16 bits 8 bits (5 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? 16 bits 8 bits (8 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? oscillator circuits ? rc oscillator circuit (internal) : for system clock ? cf oscillator circuit : for system clock with internal rf ? crystal oscillator circuit : for low-spee d system clock with external rd and rf ? multifrequency oscillator circuit (internal) : for system clock
lc87f6ac8a no.a0145-5/34 ? system clock divider function ? capable of run the minimum instruction cycle time can be selected from among 300ns, 600ns, 1.2 s, 2.4 s, 4.8 s, 9.6 s, 19.2 s, 38.4 s, and 76.8 s (at a main clock rate of 10mhz).ning on low current. ? clock output function <1> capable of generating 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, or 1/64 of the source clock that is selected as the system clock. <2> capable of generating the source clock for the subclock. ? standby function ? halt mode: halts instruction execution while allowing the peripheral circuits to continue operation. (the vfd display function and part of the serial transfer functions are disabled.) <1> oscillation is not halted automatically. <2> released by system reset or occurrence of an interrupt. ? hold mode: suspends instruction execution and operation of the peripheral circuits. <1> the cf oscillator, rc oscillator, crystal oscillator, and multifrequency rc oscillator automatically stop operation. <2> there are three ways of releasing hold mode: 1) setting the reset pin to a low level 2) setting at least one of the int0, int1, int2, int4, and int5 pins to the specified level 3) establishing an interrupt source at port 0 ? x?tal hold mode: suspends instruction execution and the op eration of the peripheral circuits except the base timer. <1> the cf oscillator, rc oscillator, and multifrequ ency rc oscillator automatically stop operation. <2> the crystal oscillator retains the stat e when x?tal hold mode is entered. <3> there are four ways of releasing x?tal hold mode: 1) setting the reset pin to a low level 2) setting at least one of the int0, int1, int2, int4, and int5 pins to the specified level 3) establishing an interrupt source at port 0 4) establishing an interrupt source in the base timer circuit ? on-chip debugger function ? supports software debugging with the microcontroller mounted on the target device ? development tools ? evaluation chip: lc87ev690 ? flash rom programming board: w87fq100 user option selection emulator lc876a00 series compatible eva62s + ecb876600d + sub876a00 + pod100qfp ice-b877300 + sub876a00 + pod100qfp lc876b00 series compatible eva62s + ecb876600d + sub876b00 + pod100qfp ice-b877300 + sub876b00 + pod100qfp ? same package and pin assignment as mask rom version ? the lc87f6ac8a allows the user to specify the optio nal functions of the lc876a00 or lc876b00 series microcontrollers in the form of flash rom data (note, however, that pins s32 to s47 are not provided with an internal pull-down resistor). this makes it possible to conduct sample tests using the production model circuit board. ? when a program that is designed for the mask rom version is applied to the lc87f6ac8a, the size of rom and ram that can be used is the same as that of the mask rom version of the microcontrtoller.
lc87f6ac8a no.a0145-6/34 package dimensions unit : mm pqfp100 14x20 / qip100e case 122bv issue a xxxxx = specific device code y = year m = month ddd = additional traceability data generic marking diagram* *this information is generic. please refer to device data sheet for actual part marking. xxxxxxxxx ymddd (unit: mm) 22.30 16.30 0.43 0.65 1.30 soldering footprint* note: the measurements are not to guarantee but for reference only. *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. 20.0 0.1 12 0.65 (0.58) 0.13 14.0 0.1 17.2 0.2 23.2 0.2 100 0.3 0.05 0.10 3.0 max (2.7) 0.1 0.1 0~10 0.15 +0.15 0.05 0.8 0.2
lc87f6ac8a no.a0145-7/34 pin assignment * lc876a00 series compat ible configuration qip100e (lead/halogen free type) s19/pc3 s18/pc2 s17/pc1 s16/pc0 v dd 3 s15/t15 s14/t14 s13/t13 s12/t12 s11/t11 s10/t10 s9/t9 s8/t8 s7/t7 s6/t6 s5/t5 s4/t4 s3/t3 s2/t2 s1/t1 pa0 pa1 pa2 pa3 p00 p01 p02 p03 v ss 2 v dd 2 p04 p05/cko p06/t6o p07/t7o p10/so0 p11/si0/sb0 p12/sck0 p13/so1 p14/si1/sb1 p15/sck1 p16/t1pwml/an14 p17/t1pwmh/buz p30/int4/t1in/int6/t0lcp1/pwm4 p31/int4/t1in/pwm5 p32/int4/t1in p33/int4/t1in p34/int5/t1in/int7/t0hcp1 p35/int5/t1in p36/int5/t1in/an12 p37/int5/t1in/an13 res xt1/an10 xt2/an11 v ss 1 cf1 cf2 v dd 1 p80/an0 p81/an1 p82/an2 p83/an3 p84/an4 p85/an5 p86/an6 p87/an7/micin p70/int0/t0lcp/an8 p71/int1/t0hcp/an9 p72/int2/t0in/nkin p73/int3/t0in s0/t0 s47/pf7 s46/pf6 s45/pf5 s44/pf4 s43/pf3 s42/pf2 s41/pf1 s40/pf0 v dd 4 s39/pe7 s38/pe6 s37/pe5 s36/pe4 s35/pe3 s34/pe2 s33/pe1 s32/pe0 s31/pd7 s30/pd6 s29/pd5 s28/pd4 s27/pd3 s26/pd2 s25/pd1 s24/pd0 s23/pc7 s22/pc6 s21/pc5 s20/pc4 vp 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
lc87f6ac8a no.a0145-8/34 pin assignment * lc876b00 series compat ible configuration qip100e (lead/halogen free type) s19/pc3 s18/pc2 s17/pc1 s16/pc0 v dd 3 s15/t15 s14/t14 s13/t13 s12/t12 s11/t11 s10/t10 s9/t9 s8/t8 s7/t7 s6/t6 s5/t5 s4/t4 s3/t3 s2/t2 s1/t1 pa0 pa1 pa2 pa3 p00 p01 p02 p03 v ss 2 v dd 2 p04 p05/cko p06/t6o p07/t7o p10/so0 p11/si0/sb0 p12/sck0 p13/so1 p14/si1/sb1 p15/sck1 p16/t1pwml/an14 p17/t1pwmh/buz si2p0/so2/int4/t1in/int6/t0lcp1 si2p1/si2/sb2/int4/t1in p32/int4/t1in p33/int4/t1in p34/int5/t1in/int7/t0hcp1 p35/int5/t1in si2p2/sck2/int5/t1in/an12 si2p3/sck2o/int5/t1in/an13 res xt1/an10 xt2/an11 v ss 1 cf1 cf2 v dd 1 p80/an0 p81/an1 p82/an2 p83/an3 p84/an4 p85/an5 p86/an6 p87/an7/micin p70/int0/t0lcp/an8 p71/int1/t0hcp/an9 p72/int2/t0in/nkin p73/int3/t0in s0/t0 s47/pf7 s46/pf6 s45/pf5 s44/pf4 s43/pf3 s42/pf2 s41/pf1 s40/pf0 v dd 4 s39/pe7 s38/pe6 s37/pe5 s36/pe4 s35/pe3 s34/pe2 s33/pe1 s32/pe0 s31/pd7 s30/pd6 s29/pd5 s28/pd4 s27/pd3 s26/pd2 s25/pd1 s24/pd0 s23/pc7 s22/pc6 s21/pc5 s20/pc4 vp 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
lc87f6ac8a no.a0145-9/34 system block diagram * lc876a00 series com patible configuration alu interrupt control standby control ir pla flash rom pc bus interface port 0 port 1 sio1 timer 0 (hi-speed clock counter) timer 1 base timer vfd display controlle r int0 to int7 noise filter port 3 port 7 port 8 port a adc acc b register c register psw rar ram stack pointer wtachdog timer small signal detector timer 4 sio0 pwm4, 5 clock generator cf rc mrc x?tal timer 6 timer 5 timer 7 timer 8 on-chip debugger
lc87f6ac8a no.a0145-10/34 system block diagram * lc876b00 series com patible configuration alu interrupt control standby control ir pla flash rom pc bus interface port 0 port 1 sio1 sio2 timer 0 (hi-speed clock counter) timer 1 base timer vfd display controlle r int0 to int7 noise filter port 3 port 7 port 8 port a adc acc b register c register psw rar ram stack pointer watchdog timer small signal detector timer 4 sio0 clock generator cf rc mrc x?tal timer 6 timer 5 timer 7 timer 8 on-chip debugger
lc87f6ac8a no.a0145-11/34 pin description * common to lc876a00 and lc876b00 compatible series pin name i/o description option v ss 1, v ss 2 ? ? power supply pin no v dd 1, v dd 2 v dd 3, v dd 4 ? + power supply pin no vp ? ? vfd power supply pin no port 0 p00 to p07 i/o ? 8-bit input/output port ? input/output can be specified in 4-bit units. ? pull-up registers can be turned on and off in 4-bit units. ? hold release input ? port 0 interrupt input ? 12v maximum withstand voltage in n-channel open drain output mode ? multiplexed pin functions p05: clock output (system clock/subclock selectable) p06: timer 6 toggle output p07: timer 7 toggle output yes port 1 p10 to p17 i/o ? 8-bit input/output port ? input/output can be specified in 1-bit units. ? pull-up registers can be turned on and off in 1-bit units. ? multiplexed pin functions p10: sio0 data output p11: sio0 data inpu t / bus input/output p12: sio0 clock input/output p13: sio1 data output p14: sio1 data inpu t / bus input/output p15: sio1 clock input/output p16: timer 1 pwml output ad converter input port (an14) p17: timer 1 pwmh output/buzzer output yes port 7 p70 to p73 i/o ? 4-bit input/output port ? input/output can be specified in 1-bit units. ? pull-up registers can be turned on and off in 1-bit units. ? multiplexed pin functions p70: int0 input/hold release input/timer 0l capture input/watchdog timer output p71: int1 input/hold release input/timer 0h capture input p72: int2 input/hold release input/timer 0 event input/timer 0l capture input/ high-speed clock counter input p73: int3 input (input with noise filter) /timer 0 event input/timer 0h capture input ad converter input port: an8(p70), an9(p71) ? interrupt acknowledge type rising falling falling & rising h level l level int0 int1 int2 int3 no port 8 p80 to p87 i/o ? 8-bit input/output port ? input/output can be specified in 1-bit units. ? multiplexed pin functions ad converter input port: an0 to an7 small signal detector input port: micin (p87) no
lc87f6ac8a no.a0145-12/34 pin name i/o description option s0/t0 to s8/t8 o ? large current output for vac uum fluorescent display (vfd) controller digits (also can be used as segment outputs) no s9/t9 to s15/t15 o ? large current output for vacuum fluorescent display (vfd) controller segments/digits no s16 to s23 i/o ? output for vacuum fluoresce nt display (vfd) cont roller segments/digits ? multiplexed pin functions high withstand voltage input port: pc0 to pc7 no s24 to s31 i/o ? output for vacuum fluor escent display (vfd) controller segments ? multiplexed pin functions high withstand voltage input port: pd0 to pd7 no s32 to s39 i/o ? output for vacuum fluor escent display (vfd) controller segments ? multiplexed pin functions high withstand voltage input port: pe0 to pe7 yes (not available for flash rom version) s40 to s47 i/o ? output for vacuum fluor escent display (vfd) controller segments ? multiplexed pin functions high withstand voltage input/output port: pf0 to pf7 yes (not available for flash rom version) port pa0 to pa3 i/o ? 4-bit input/output port ? input/output can be specified in 1-bit units ? pull-up registers can be turned on and off in 1-bit units. ? multiplexed pin functions on-chip debugger control function: pa01 to pa03 yes ____ res i reset pin no xt1 i ? 32.768khz crystal resonator input pin ? multiplexed pin functions general-purpose input port must be connected to vdd1 when not to be used. ad converter input port: an10 no xt2 i/o ? 32.768khz crystal resonator output pin ? multiplexed pin functions general-purpose input/output port must be configured for oscillation and held open when not to be used. ad converter input port: an11 no cf1 i ceramic resonator input pin no cf2 o ceramic resonator output pin no
lc87f6ac8a no.a0145-13/34 * lc876a00 series comp atible configuration pin name i/o description option port 3 p30 to p37 i/o ? 8-bit input/output port ? input/output can be specified in 1-bit units. ? pull-up registers can be turned on and off in 1-bit units. ? multiplexed pin functions p30: pwm4 output/int6 input p31: pwm5 output p30 to p33: int4 input/hold re lease input/timer 1 event input/ timer 0l capture input/timer 0h capture input p34: int7 input p34 to p37: int5 input/hold re lease input/timer 1 event input/ timer 0l capture input/timer 0h capture input ad converter input port: an12 (p36), an13(p37) ? interrupt acknowledge type rising falling falling & rising h level l level int4 int5 int6 int7 yes * lc876b00 series compatible configuration pin name i/o description option port 3 p30 to p37 i/o ? 4-bit input/output port ? input/output can be specified in 1-bit units ? pull-up registers can be turned on and off in 1-bit units. ? multiplexed pin functions p32 to p33: int4 input/hold re lease input/timer 1 event input/ timer 0l capture input/timer 0h capture input p34: int7 input p34 to p35: int5 input/hold re lease input/timer 1 event input/ timer 0l capture input/timer 0h capture input ? interrupt acknowledge type rising falling falling & rising h level l level int4 int5 int6 int7 yes sio2 port si2p0 to si2p3 i/o ? 4-bit input/output port ? input/output can be specified in 1-bit units ? multiplexed pin functions si2p0: sio2 data output/int6 input si2p1: sio2 data input / bus input/output si2p2: sio2 clock input/output si2p3: sio2 clock output si2p0 to si2p1: int4 input/hold release input/timer1 event input/ timer 0l capture input/timer 0h capture input si2p2 to si2p3: int5 input/hold release input/timer1 event input/ timer 0l capture input/timer 0h capture input ad converter input port: an12 (si2p2), an13(si2p3) ? see the table above for port 3 for the interrupt acknowledge type for sio2 ports. yes
lc87f6ac8a no.a0145-14/34 port output types the tables below list the types of port outputs and the presence/absence of a pull-up resistor. data can be read into any input/output port even if it is in output mode. * common to the lc876a00 and lc876b00 compatible series port name option selected in units of option type output type pull-up resistor pull-down resistor 1 cmos programmable (note 1) ? p00 to p07 1 bit 2 12v withstand voltage n-channel open drain no ? 1 cmos programmable ? p10 to p17 1 bit 2 n-channel open drain programmable ? p70 ? no n-channel open drain programmable ? p71 to p73 ? no cmos programmable ? p80 to p87 ? no n-channel open drain no ? s0/t0 to s15/t15 s16 to s31 ? no high withstand voltage p-channel open drain ? fixed 1 high withstand voltage p-channel open drain ? fixed s32 to s47 (note 2) 1 bit 2 high withstand voltage p-channel open drain ? no 1 cmos programmable ? pa0 to pa3 1 bit 2 n-channel open drain programmable ? xt1 ? no input only no ? xt2 ? no 32.768khz crystal resonator output (n-channel open drain when selecting general-purpose output port) no ? * lc876a00 series comp atible configuration port name option selected in units of option type output type pull-up resistor pull-down resistor 1 cmos programmable ? p30 to p37 1 bit 2 n-channel open drain programmable ? * lc876b00 series compatible configuration port name option selected in units of option type output type pull-up resistor pull-down resistor 1 cmos programmable ? p32 to p35 1 bit 2 n-channel open drain programmable ? si2p0 to si2p3 ? no cmos (si2p1: n-channel open drain when selecting sio2 data) no ? note 1: the control of the presence or absence of the programm able pull-up resistors for port 0 is exercised in 4-bit units (p00 to p03, p04 to p07). note 2: a built-in internal pull-down resistor can be connected to s32 to s47 in 1-bit units (with a mask option) only for the mask rom version of product. the flash rom version (lc87f6ac8a) does not include the internal pull-down resistor.
lc87f6ac8a no.a0145-15/34 *1 make the following connection to minimize the noise input to the v dd 1 pin and prolong the backup time. be sure to electrically short the v ss 1and v ss 2 pins. *2 the internal memory is sustained by v dd 1. if v dd 2 is not backed up, the high-level output at the ports are unstable in hold backup mode, allowing through current to flow in to the input buffer and thus shortening the backup time. make sure that the port outputs are held at a low level in hold backup mode. power supply i c v dd 1 backup capacitors *2 v dd 2 v dd 3 v ss 2 v ss 1 v dd 4 vfd power supply
lc87f6ac8a no.a0145-16/34 1. absolute maximum ratings at ta = 25 c, v ss 1 = v ss 2 = 0v specification parameter symbol pin/remarks conditions v dd [v] min. typ. max. unit maximum supply voltage v dd max v dd , v dd 2, v dd 3, v dd 4 v dd 1=v dd 2=v dd 3 =v dd 4 -0.3 to +6.5 v i (1) ?xt1 ?cf1 ? ____ res -0.3 to v dd +0.3 input voltage v i (2) vp v dd -45 to v dd +0.3 output voltage v o (1) s0/t0 to s15/t15 v dd -45 to v dd +0.3 v io (1) ?cmos output p0 ?p1, p7, p8, pa ?p30 to p37 (lc876a00 compatible) ?p32 to p35 / si2p0 to si2p3 (lc876b00 compatible ) ?xt2 -0.3 to v dd +0.3 v io (2) open drain output p0 -0.3 to 12 input/output voltage v io (3) s16 to s47 v dd -45 to v dd +0.3 v ioph(1) ?p0, p1, pa ?p30 to p37 (lc876a00 compatible) ?p32 to p35 / si2p0 to si2p3 (lc876b00 compatible) ?cmos output ?per 1 applicable pin -10 ioph(2) p71 to p73 per 1 applicable pin -3 ioph(3) s0/t0 to s15/t15 per 1 applicable pin -30 peak output current ioph(4) s16 to s47 per 1 applicable pin -15 ioah(1) ?p00 to p03 ?pa total current of all applicable pins -30 ioah(2) ?p04 to p07 ?p1 ?p30 to p37 (lc876a00 compatible) ?p32 to p35 / si2p0 to si2p3 (lc876b00 compatible) total current of all applicable pins -30 ioah(3) p71 to p73 total current of all applicable pins -5 ioah(4) s0/t0 to s15/t15 total current of all applicable pins -65 ioah(5) s16 to s27 total current of all applicable pins -60 ioah(6) s28 to s39 total current of all applicable pins -60 high level output current total output current ioah(7) s40 to s47 total current of all applicable pins -60 ma continued on next page.
lc87f6ac8a no.a0145-17/34 continued from preceding page. specification parameter symbol pin/remarks conditions v dd [v] min. typ. max. unit iopl(1) ?p0, p1, pa ?p30 to p37 (lc876a00 compatible) ?p32 to p35 / si2p0 to si2p3 (lc876b00 compatible) per 1 applicable pin 20 peak output current iopl(2) ?p7, p8 ?xt2 per 1 applicable pin 5 ioal(1) ?p00 to p03, pa total current of all applicable pins 50 ioal(2) ?p04 to p07 ?p1 ?p30 to p37 (lc876a00 compatible ) ?p32 to p35 / si2p0 to si2p3 (lc876b00 compatible) total current of all applicable pins 50 low level output current total output current ioal(3) ?p7, p8 ?xt2 total current of all applicable pins 20 ma allowable power dissipation pd max qip100e ta=-20 to +70 c 508 mw operating ambient temperature topr -20 to +70 storage ambient temperature tstg -55 to +125 c note: the applicable pins (si2pn or p30, p31, p36, and p37) vary depending on the user options selected. check the pin assignment diagram of the selected product type (lc876a00 or lc876b00). stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should n ot be assumed, damage may occur and reliability may be affected.
lc87f6ac8a no.a0145-18/34 2. allowable operating range at ta = -20 to +70 c, v ss 1 = v ss 2 = 0v specification parameter symbol pin/remarks conditions v dd [v] min. typ. max. unit v dd (1) 0.250 s tcyc 200 s 2.8 5.5 operating supply voltage (note 1) v dd (2) v dd 1=v dd 2=v dd 3=v dd 4 0.735 s tcyc 200 s 2.5 5.5 memory sustaining supply voltage vhd v dd 1 ?in hold mode ?ram and register contents sustained 2.0 5.5 pull-down supply voltage vp vp -35 v dd v ih (1) ?cmos output p0 ?p8, pa output disabled 2.5 to 5.5 0.3v dd +0.7 v dd v ih (2) open drain output type p0 output disabled 2.5 to 5.5 0.3v dd +0.7 11 v ih (3) ?p1 ?p30 to p37 (lc876a00 compatible) ?p32 to p35 / si2p0 to si2p3 (lc876b00 compatible) ?p71, 72, 73 ?p70 port input/ interrupt side output disabled 2.5 to 5.5 0.3v dd +0.7 v dd v ih (4) s16 to s47 output p-channel tr off 2.5 to 5.5 0.33v dd +1.0 v dd v ih (5) ?p87 small signal input side output disabled 2.5 to 5.5 0.75v dd v dd v ih (6) ?p70 watchdog timer side output disabled 2.5 to 5.5 0.9v dd v dd high level input voltage v ih (7) ?xt1, xt2 ?cf1, ____ res 2.5 to 5.5 0.75v dd v dd v il (1) ?p0, p8, pa output disabled 2.5 to 5.5 v ss 0.15v dd +0.4 v il (2) ?p1 ?p30 to p37 (lc876a00 compatible) ?p32 to p35 / si2p0 to si2p3 (lc876b00 compatible) ?p71 to p73 ?p70 port input/interrupt side output disabled 2.5 to 5.5 v ss 0.1v dd +0.4 v il (3) s16 to s47 output p-channel tr off 2.5 to 5.5 -35 0.2v dd v il (4) ?p87small signal input side output disabled 2.5 to 5.5 v ss 0.25v dd v il (5) ?p70 watchdog timer side output disabled 2.5 to 5.5 v ss 0.8v dd -1.0 low level input voltage v il (6) ?xt1, xt2 ?cf1, ____ res 2.5 to 5.5 v ss 0.25v dd v 3.0 to 5.5 0.250 200 instruction cycle time (note 1) tcyc 2.5 to 5.5 0.735 200 s continued on next page.
lc87f6ac8a no.a0145-19/34 continued from preceding page. specification parameter symbol pin/remarks conditions v dd [v] min. typ. max. unit 2.8 to 5.5 0.1 12 ?cf2 pin open ?system clock frequency division ratio=1/1 ?external system clock duty= 505% 2.5 to 5.5 0.1 4 2.8 to 5.5 0.2 24 external system clock frequency fexcf(1) cf1 ?cf2 pin open ?system clock frequency division ratio=1/2 ?external system clock duty= 505% 2.5 to 5.5 0.2 8 mhz fmcf(1) cf1, cf2 12mhz ceramic oscillation mode see fig. 1. 2.8 to 5.5 12 fmcf(2) cf1, cf2 4mhz ceramic oscillation mode see fig. 1. 2.5 to 5.5 4 fmrc internal rc oscillation 2.5 to 5.5 0.3 1.0 2.0 fmmrc multifrequency rc oscillator source oscillation 2.5 to 5.5 18 mhz oscillation frequency range (note 2) fsx?tal xt1, xt2 32.768khz crystal oscillation mode see fig. 2. 2.5 to 5.5 32.768 khz note 1: onboard programming is possible when v dd 4.5[v]. note 2: see table 1 and table 2 for the oscillation constant. functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresses beyond the recomme nded operating ranges limits may affect device r eliab ility.
lc87f6ac8a no.a0145-20/34 3. electrical characteristics at ta = -20 to +70 c, v ss 1 = v ss 2 = 0v specification parameter symbol pin/remarks conditions v dd [v] min. typ. max. unit i ih (1) open drain output type p0 ?output disabled ?v in =11v (including output tr?s off leakage current) 2.5 to 5.5 5 i ih (2) ?p0, p1, p7, p8, pa ?p30 to p37 (lc876a00 compatible) ?p32 to p35, si2p0 to si2p3 (lc876b00 compatible) ?output disabled ?pull-up resistor off ?v in =v dd (including output tr?s off leakage current) 2.5 to 5.5 1 i ih (3) s16 to s47 (pc, pd, pe, pf) ?in input port mode ?v in =v dd 2.5 to 5.5 60 i ih (4) ____ res v in =v dd 2.5 to 5.5 1 i ih (5) xt1, xt2 ?in input port mode ?v in =v dd 2.5 to 5.5 1 i ih (6) cf1 v in =v dd 2.5 to 5.5 15 4.5 to 5.5 4.2 8.5 15 high level input current i ih (7) p87/an7/micin small signal input side v in =vbis+0.5v (vbis is a bias voltage.) 2.5 to 4.5 1.5 5.5 10 i il (1) ?p0, p1, p7, p8, pa ?p30 to p37 (lc876a00 compatible) ?p32 to p35, si2p0 to si2p3 (lc876b00 compatible) ?output disabled ?pull-up resistor off ?v in =v ss (including output tr?s off leakage current) 2.5 to 5.5 -1 i il (2) ____ res v in =v ss 2.5 to 5.5 -1 i il (3) xt1, xt2 ?in input port mode ?v in =v ss 2.5 to 5.5 -1 i il (4) cf1 v in =v ss 2.5 to 5.5 -15 4.5 to 5.5 -15 -8.5 -4.2 low level input current i il (5) p87/an7/micin small signal input side v in =vbis-0.5v (vbis is a bias voltage.) 2.5 to 4.5 -10 -5.5 -1.5 a v oh (1) i oh =-1.0ma 4.5 to 5.5 v dd -1 v oh (2) i oh =-0.5ma 3.0 to 5.5 v dd -1 v oh (3) ?cmos output type p0 ?p1 ?p30 to p37 (lc876a00 compatible) ?pwm4, pwm5 (lc876a00 compatible) ?p32 to p35, si2p0 to si2p3 (lc876b00 compatible) i oh =-0.1ma 2.5 to 5.5 v dd -0.5 v oh (4) p71 to p73 i oh =-0.4ma 2.5 to 5.5 v dd -1 v oh (5) i oh =-20ma 4.5 to 5.5 v dd -1.8 v oh (6) i oh =-10ma 3.0 to 5.5 v dd -1.8 v oh (7) s0/t0 to s15/t15 ?i oh =-1.0ma ?when per pin i oh of all pins is 1ma or less 2.5 to 5.5 v dd -1 v oh (8) i oh =-5.0ma 4.5 to 5.5 v dd -1.8 v oh (9) i oh =-2.5ma 3.0 to 5.5 v dd -1.8 high level output voltage v oh (10) s16 to s47 ?i oh =-1.0ma ?when per pin i oh of all pins is 1ma or less 2.5 to 5.5 v dd -1 v continued on next page.
lc87f6ac8a no.a0145-21/34 continued from preceding page. specification parameter symbol pin/remarks conditions v dd [v] min. typ. max. unit v ol (1) i ol =10ma 4.5 to 5.5 1.5 v ol (2) i ol =5ma 3.0 to 5.5 1.5 v ol (3) ?p0, p1, pa ?p30 to p37 (lc876a00 compatible) ?p32 to p35, si2p0 to si2p3 (lc876b00 compatible) i ol =1.6ma 2.5 to 5.5 0.4 v ol (4) i ol =1.0ma 4.5 to 5.5 1.0 v ol (5) i ol =0.5ma 3.0 to 5.5 1.0 v ol (6) ?p30 to p31 (lc876a00 compatible: when pwm4/5 is used) i ol =0.1ma 2.5 to 5.5 0.5 low level output voltage v ol (7) ? ports 7, 8 ?xt2 i ol =1ma 2.5 to 5.5 0.4 v 4.5 to 5.5 15 40 70 pull-up mos-tr resistance rpu ports 0, 1, 7, a ?p30 to p37 (lc876a00 compatible) ?p32 to p35 (lc876b00 compatible) v oh =0.9v dd 2.5 to 4.5 25 70 150 k ioff (1) ?output p-channel tr off ?v out =v ss 2.5 to 5.5 -1 output off leakage current ioff (2) ?s0/t0 to s15/t15 ?s16 to s47 ?output p-channel tr off ?v out =v dd -40v 2.5 to 5.5 -30 a high withstand voltage input pin l level hold tr. rinpd s16 to s47 output p-channel tr off 2.5 to 5.5 200 high withstand voltage pull-down resistance rpd pull-down resistor present ?s0/t0 to s15/t15 ?s16 to s47 ?output p-channel tr off ?v out =3v ?vp=-30v 5.0 60 100 200 k vhis(1) ?p1, p3, p7 ?p30 to p37 (lc876a00 compatible) ?p32 to p35, si2p0 to si2p3 (lc876b00 compatible) ? ____ res 2.5 to 5.5 0.1v dd hysteresis voltage vhis(2) ?p87 small signal input side 2.5 to 5.5 0.1v dd v pin capacitance cp all pins ?f=1mhz ?for the pin other than that under test v in =v ss ?ta=25 c 2.5 to 5.5 10 pf input sensitivity vsen ?p87 small si gnal input side 2.5 to 5.5 0.12v dd vpp product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product per formance may not be indicated by the electrical characteristics if operated under different conditions.
lc87f6ac8a no.a0145-22/34 4. serial i/o characteristics at ta = -20 to +70 c, v ss 1 = v ss 2 = 0v specification parameter symbol pin/remarks conditions v dd [v] min. typ. max. unit period tsck(1) 2.5 to 5.5 4/3 tsckl(1) 2.5 to 5.5 2/3 low level pulse width tsckla(1) 2.5 to 5.5 2/3 tsckh(1) 2.5 to 5.5 2/3 high level pulse width tsckha(1) sck0(p12) sck2(si2p2) (lc876b00 compatible) see fig. 6. 2.5 to 5.5 5 period tsck(2) 2.5 to 5.5 2 low level pulse width tsckl(2) 2.5 to 5.5 1 input clock high level pulse width tsckh(2) sck1(p15) see fig. 6. 2.5 to 5.5 1 period tsck(3) 2.5 to 5.5 4/3 tcyc tsckl(3) ?cmos output type selected ?see fig. 6. 2.5 to 5.5 1/2 sck(p12) for sio0 3/4 low level pulse width tsckla(2) si2p2, si2p3 for sio2 2.5 to 5.5 1 tsckh(3) 2.5 to 5.5 1/2 sck(p12) for sio0 2 high level pulse width tsckha(2) sck0(p12) sck2(si2p2), sck2o(si2p3) (lc876b00 compatible) si2p2, si2p3 for sio2 2.5 to 5.5 7/4 tsck period tsck(4) 2.5 to 5.5 2 tcyc low level pulse width tsckl(4) 2.5 to 5.5 1/2 serial clock output clock high level pulse width tsckh(4) sck1(p15) ?cmos output type selected ?see fig. 6. 2.5 to 5.5 1/2 tsck 4.5 to 5.5 0.03 3.0 to 4.5 0.05 data setup time tsdi 2.5 to 3.0 0.1 4.5 to 5.5 0.03 3.0 to 4.5 0.05 serial input data hold time thdi si0(p11), si1(p14), sb0(p11), sb1(p14) si2(si2p1), sb2(si2p1) (lc876b00 compatible) ?specified with respect to the rising edge of sioclk. ?see fig. 6. 2.5 to 3.0 0.1 3.0 to 5.5 1/3 tcyc +0.05 serial output output delay time tddo so0(p10), so1(p13), sb0(p11), sb1(p14) so2(si2p0), sb2(si2p1) (lc876b00 compatible) ?specified with respect to the falling edge of sioclk. ?specified as the time up to the beginning of output change in open drain output mode. ?see fig. 6. 2.5 to 3.0 1/3 tcyc +0.15 s note: the sio2 function is available only when the lc876b00 series compatible configura tion is selected as a user option.
lc87f6ac8a no.a0145-23/34 5. pulse input conditions at ta = -20 to +70 c, v ss 1 = v ss 2 = 0v specification parameter symbol pin/remarks conditions v dd [v] min. typ. max. unit tpih(1) tpil(1) int0(p70), int1(p71), int2(p72) ?interrupt source flag can be set. ?event input to timers 0 and 1 is enabled. 2.5 to 5.5 1 ?int4(p30 to p33) ?int5(p34 to p37) ?int6(p30) ?int7(p34) (lc876a00 compatible) tpih(2) tpil(2) ?int4(si2p0, si2p1, p32, p33) ?int5(p34, p35, si2p2, si2p3) ?int6(si2p0) ?int7(p34) (lc876b00 compatible) ?interrupt source flag can be set. ?event input to timers 0 and 1 is enabled. 2.5 to 5.5 1 tpih(3) tpil(3) int3(p73) when noise filter time constant is 1/1 ?interrupt source flag can be set. ?event input to timer 0 is enabled. 2.5 to 5.5 2 tpih(4) tpil(4) int3(p73) when noise filter time constant is 1/32 ?interrupt source flag can be set. ?event input to timer 0 is enabled. 2.5 to 5.5 64 tpih(5) tpil(5) int3(p73) when noise filter time constant is 1/128 ?interrupt source flag can be set. ?event input to timer 0 is enabled. 2.5 to 5.5 256 tpih(6) tpil(6) micin(p87) small signal detection counter counted 2.5 to 5.5 1 tpih(7) tpil(7) nkin(p72) high-speed clock count er counted 2.5 to 5.5 1/12 tcyc high/low level pulse width tpil(8) ____ res reset is enabled. 2.5 to 5.5 200 s
lc87f6ac8a no.a0145-24/34 6. ad converter characteristics at ta = -20 to +70 c, v ss 1 = v ss 2 = 0v specification parameter symbol pin/remarks conditions v dd [v] min. typ. max. unit resolution n 3.0 to 5.5 8 bit absolute precision et (note 3) 3.0 to 5.5 1.5 lsb 4.5 to 5.5 15.62 (tcyc= 0.488 s) 97.92 (tcyc= 3.06 s) ad conversion time=32 tcyc (when adcr2=0) (note 4) 3.0 to 5.5 23.52 (tcyc= 0.735 s) 97.92 (tcyc= 3.06 s) 4.5 to 5.5 18.82 (tcyc= 0.294 s) 97.92 (tcyc= 1.53 s) conversion time tcad ad conversion time=64 tcyc (when adcr2=1) (note 4) 3.0 to 5.5 47.04 (tcyc= 0.735 s) 97.92 (tcyc= 1.53 s) s analog input voltage range vain 3.0 to 5.5 v ss v dd v iainh vain=v dd 3.0 to 5.5 1 analog port input current iainl ?an0(p80) to an7(p87), an8(p70), an9(p71), an10(xt1), an11(xt2) ?an12, an13(p36, p37) (lc876a00 compatible) ?an12, an13 (si2p2, si2p3) (lc876b00 compatible) ?an14 (p16) vain=v ss 3.0 to 5.5 -1 a note 3: the quantization error (1/2lsb) is excluded from the absolute accuracy. note 4: the conversion time refers to the interval from the time a conversion starting instruction is issued until the time the complete digital value corresponding to the analog input value is loaded in the register.
lc87f6ac8a no.a0145-25/34 7. consumption current characteristics at ta = -20 to +70 c, v ss 1 = v ss 2 = 0v specification parameter symbol pin/remarks conditions v dd [v] min. typ. max. unit 4.5 to 5.5 7.9 24 iddop(1) ?fmcf=12mhz ceramic oscillation ?fsx?tal=32.768khz crystal oscillation ?system clock set to 12mhz side ?internal rc oscillation stopped ?frequency division ratio set to 1/1 2.8 to 4.5 3.8 14 4.5 to 5.5 7.8 22 iddop(2) ?cf1=20mhz external clock ?fsx?tal=32.768khz crystal oscillation ?system clock set to cf1 side ?internal rc oscillation stopped ?frequency division ratio set to 1/2 2.8 to 4.5 3.5 12 4.5 to 5.5 4.8 14 iddop(3) ?fmcf=4mhz ceramic oscillation ?fsx?tal=32.768khz crystal oscillation ?system clock set to 4mhz side ?internal rc oscillation stopped ?frequency division ratio set to 1/1 2.5 to 4.5 2.4 6 4.5 to 5.5 1.6 10 iddop(4) ?fmcf=0hz (oscillation stopped) ?fsx?tal=32.768khz crystal oscillation ?internal rc oscillation stopped ?system clock set to internal multifrequency oscillator rc oscillator set to 1mhz ?frequency division ratio set to 1/2 2.5 to 4.5 0.7 4 4.5 to 5.5 0.85 4 iddop(5) ?fmcf=0hz (oscillation stopped) ?fsx?tal=32.768khz crystal oscillation ?system clock set to internal rc oscillator ?frequency division ratio set to 1/2 2.5 to 4.5 0.35 3 ma 4.5 to 5.5 290 1100 normal mode consumption current (note 5) iddop(6) v dd 1 =v dd 2 =v dd 3 =v dd 4 ?fmcf=0hz (oscillation stopped) ?fsx?tal=32.768khz crystal oscillation ?system clock set to 32.768khz side ?internal rc oscillation stopped ?frequency division ratio set to 1/2 2.5 to 4.5 96.0 400 a continued on next page.
lc87f6ac8a no.a0145-26/34 continued from preceding page. specification parameter symbol pin/remarks conditions v dd [v] min. typ. max. unit 4.5 to 5.5 3.4 10 iddhalt(1) ?halt mode ?fmcf=12mhz ceramic oscillation ?fsx?tal=32.768khz crystal oscillation ?system clock set to 12mhz side ?internal rc oscillation stopped ?frequency division ratio set to 1/1 2.8 to 4.5 1.3 6 4.5 to 5.5 3.9 10 iddhalt(2) ?halt mode ?cf1=20mhz external clock ?fsx?tal=32.768khz crystal oscillation ?system clock set to cf1 side ?internal rc oscillation stopped ?frequency division ratio set to 1/2 2.8 to 4.5 1.5 6 4.5 to 5.5 1.6 4 iddhalt(3) ?halt mode ?fmcf=4mhz ceramic oscillation ?fsx?tal=32.768khz crystal oscillation ?system clock set to 4mhz side ?internal rc oscillation stopped ?frequency division ratio set to 1/1 2.5 to 4.5 0.7 3 ma 4.5 to 5.5 1000 3000 iddhalt(4) ?halt mode ?fmcf=0hz (oscillation stopped) ?fsx?tal=32.768khz crystal oscillation ?internal rc oscillation stopped ?system clock is internal multifrequency rc oscillator set to 1mhz ?frequency division ratio set to 1/2 2.5 to 4.5 440 2500 4.5 to 5.5 300 1200 iddhalt(5) ?halt mode ?fmcf=0hz (oscillation stopped) ?fsx?tal=32.768khz crystal oscillation ?system clock set to internal rc oscillator ?frequency division ratio set to 1/2 2.5 to 4.5 130 750 4.5 to 5.5 25 80 halt mode consumption current (note 5) iddhalt(6) v dd 1 =v dd 2 =v dd 3 =v dd 4 ?halt mode ?fmcf=0hz (oscillation stopped) ?fsx?tal=32.768khz crystal oscillation ?system clock set to 32.768khz side ?internal rc oscillation stopped ?frequency division ratio set to 1/2 2.5 to 4.5 7.4 45 4.5 to 5.5 0.04 20 hold mode consumption current iddhold(1) v dd 1 ?hold mode ?cf1=v dd or open (external clock mode) 2.5 to 4.5 0.01 15 4.5 to 5.5 22 65 timer hold mode consumption current iddhold(2) v dd 1 ?timer hold mode ?cf1=v dd or open (external clock mode) ?fsx?tal=32.768khz crystal oscillation 2.5 to 4.5 5.7 40 a note 5: the consumption current value does not include the cu rrents that flow into the output transistors and internal pull-up resistors.
lc87f6ac8a no.a0145-27/34 8. f-rom programming characteristics at ta = +10 to +55 c, v ss 1 = v ss 2 = 0v specification parameter symbol pin/remarks conditions v dd [v] min. typ. max. unit onboard programming current iddfw(1) v dd 1 ?128-byte write ?including erase current 3.0 to 5.5 25 40 ma programming time tfw(1) ?128-byte write ?including erase current ?excluding the time for setting up 128-byte data 3.0 to 5.5 22.5 45 ms
lc87f6ac8a no.a0145-28/34 9. power pin treatment conditions 1 (v dd 1, v ss 1) it is necessary to place capacitors between v dd 1 and v ss 1 as described below. ? trace length from v dd 1, v ss 1 pins to capacitors c1, c2 should be as short as possible and of the same length (l1=l1?, l2=l2?) wherever possible. ? place high capacitance capacitor c1 and lo w capacitance capacitor c2 in parallel. capacitance of c2 must be 0.1 f or more . ? v dd 1 and v ss 1 wiring traces must be thicker than other traces. 10. power pin treatment conditions 2 (v dd 2, v ss 2) it is necessary to place capacitors between v dd 2 and v ss 2 as described below. ? trace length from v dd 2, v ss 2 pins to capacitor c3 should be as short as possible and of the same length (l3=l3?) wherever possible. ? capacitance of c3 must be 0.1 f or more . ? the v dd 2 and v ss 2 wiring traces must be thicker than other traces. v ss 2 v dd 2 l3 ? l3 c3 v ss 1 v dd 1 l1 ? l2 ? l1 l2 c1 c2
lc87f6ac8a no.a0145-29/34 characteristics of a sample main system clock oscillator circuit given below are the characteristics of a sample main syst em clock oscillator circuit that are measured using our company-designated oscillation characteris tics evaluation board and external com ponents with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 1 characteristics of a sample main system clock oscillator circuit with a ceramic resonator circuit constants oscillation stabilization time nominal frequency vendor name resonator c1 [pf] c2 [pf] rd1 [ ] operating voltage range [v] typ [ms] max [ms] remarks 12mhz murata cstce12m0g52-r0 (10) (10) 470 2.8 to 5.5 0.05 0.15 c1, c2 integrated type cstls4m00g53-b0 (15) (15) 2.2k 2.5 to 5.5 0.05 0.15 4mhz murata cstcr4m00g53-r0 (15) (15) 2.2k 2.5 to 5.5 0.07 0.2 c1, c2 integrated type the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized after v dd goes above the lower limit level of the operating voltage range (see figure 4). characteristics of a sample subs ystem clock oscillator circuit given below are the characteristics of a sample subsyste m clock oscillator circuit that are measured using our company-designated oscillation characteris tics evaluation board and external com ponents with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 2 characteristics of a sample subsystem clock oscillator circuit with a crystal resonator circuit constants oscillation stabilization time nominal frequency vendor name resonator c3 [pf] c4 [pf] rf [ ] rd2 [ ] operating voltage range [v] typ [s] max [s] remarks 32.768khz epson toyocom mc-306 18 18 10m 0 2.5 to 5.5 1.5 3 applicable cl value 12.5pf the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized after the instruction for starting the subclock oscillator circuit is execut ed or the time interval that is required for the oscillation to get stabilized after hold mode is released (see figure 4). note: the components for oscillation should be placed and r outed as close to the ic as possible because they are vulnerable to the influences of the circuit pattern. figure 1 cf oscillator circuit figure 2 xt oscillator circuit figure 3 ac timing measurement point 0.5v dd c1 c2 cf cf2 cf1 rd1 c3 rd2 c4 x ? tal xt2 xt1 rf
lc87f6ac8a no.a0145-30/34 figure 4 oscillation stabilization time power su pp l y res internal rc oscillation cf1 , cf2 xt1 , xt2 o p eratin g mode reset time tmscf tmsxtal undefined reset instruction execution reset time and oscillation stabilization time internal rc oscillation cf1 , cf2 xt1 , xt2 operating mode hold release si g nal hold release signal absent hold release signal valid tmscf tmsxtal hold halt v dd operating v dd lower limit 0v hold release signal and oscillation stabilization time
lc87f6ac8a no.a0145-31/34 figure 5 reset circuit figure 6 serial i/o waveforms figure 7 pulse input timing signal waveform n ote: determine the value of cres and rres so that the reset signal is clearly present for a period of 200 s afte r the supply voltage goes beyond the lower limit of the ic?s operating voltage range. sioclk datain dataout di0 di1 di2 di3 di4 di5 di6 di7 di8 do0 do1 do2 do3 do4 do5 do6 do7 do8 data ram transfer period (sio0 and sio2 only) sioclk datain dataout tsck tsckl tsckh tsdi thdi tddo sioclk datain dataout tddo tsdi thdi tsckla tsckha data ram transfer period (sio0 and sio2 only) cres v dd rres ___ _ res tpil tpih
lc87f6ac8a no.a0145-32/34 ? difference between the lc876a00 and lc876900 series function lc876a00 series lc876900 series adc 8 bits 15 channels conversion time: 32/64/128/256 tcyc 8 bits 14 channels conversion time: 32/64 tcyc pwm pwm4/pwm5 (p30/p31multiplexed pin functions) pwm2/pwm3 (dedicated pin) port3 p30 to p37: 8 bits (no middle withstand voltage port) p32 to p37: 6 bits (p32 to p35: medium withstand voltage input support ports) no. of vfd pins 48 52 middle withstand voltage input voltage 12v max. (p0) 14v max. (p0, p32 to 35) timer 0 capture registers 2 (t0cah/t0cal, t0 cah1/t0cal1) 1 (t0cah/t0cal) timer 8 8-bit timer with 8-bit prescaler 2 channels 16-bit timer with 8-bit prescaler 2 channels external interrupt int6/int7 int6 is assigned to p30 and int7 to p34. no. of port a bits pa0 to pa3: 4 bits multifrequency rc oscillator built-in iflg list of interrupt source flag function not supported pin assignment lc876a00 series lc876900 series pin 1 p16/t1pwml/an14 p16/t1pwml pin 3 p30/int4/t1in/int6/t0lcp1/pwm4 pwm2/int4/t1in pin 4 p31/int4/t1in/pwm5 pwm3/int4/t1in pin 7 p34/int5/t1in/int7 /t0hcp1 p34/int5/t1in pin 81 pa0 s48/pg0 pin 82 pa1 s49/pg1 pin 83 pa2 s51/pg2 pin 84 pa3 s52/pg3
lc87f6ac8a no.a0145-33/34 ? difference between the lc876b00 series and lc876800 series function lc876b00 series lc876800 series adc 8 bits 15 channels conversion time: 32/64/128/256 tcyc 8 bits 14 channels conversion time: 32/64 tcyc port3 (4 bits) no middle withstand voltage port medium withstand voltage input support no. of vfd pins 48 52 middle withstand voltage input voltage 12v max. (p0) 14v max. (p0, p3) timer 0 capture resisters 2 (t0cah/t0cal, t0 cah1/t0cal1) 1 (t0cah/t0cal) timer 8 8-bit timer with 8-bit prescaler 2 channels 16-bit timer with 8-bit prescaler 2 channels external interrupt int6/int7 int6 is assigned to p0 and int7 to p34. multifrequency rc oscillator built-in no. of port a bits pa0 to pa3: 4 bits iflg list of interrupt source flag function not supported pin assignment lc876b00 series lc876800 series pin 1 p16/t1pwml/an14 p16/t1pwml pin 3 si2p0/so2/int4/t1in/int6 /t0lcp1 si2p0/so2/int4/t1in pin 7 p34/int5/t1in/int7 /t0hcp1 p34/int5/t1in pin 81 pa0 s48/pg0 pin 82 pa1 s49/pg1 pin 83 pa2 s51/pg2 pin 84 pa3 s52/pg3 ? operating voltage differences between the lc876a00/lc876b00 series and lc876800/ lc876900 series operating supply voltage lc876a00/lc876 b900 series lc876800/lc876900 series operating supply voltage/instruction cycle time 2.8 to 5.5[v] (0.252 s tcyc 200 s) 2.5 to 5.5[v] (0.735 s tcyc 200 s) except for onboard programming (v dd < 4.5v) 3.0 to 5.5[v] (0.294 s tcyc 200 s) 2.5 to 5.5[v] (0.735 s tcyc 200 s) except for onboard programming (v dd < 4.5v)
lc87f6ac8a ps no.a0145-34/34 ordering information device package shipping (qty / packing) lc87f6ac8alu-ej-h qip100e(14x20) (pb-free / halogen free) 250 / tray foam on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liab ility arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use a s components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other applica tion in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for an y such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and dis tributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona linjuryor death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale i n any manner.

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